Alif Semiconductor /AE101F4071542LH_CM55_HE_View /CLKCTL_PER_SLV /UART_CTRL

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Interpret as UART_CTRL

DMA_SEL=Val_0x0, CLK_SEL=Val_0x0, RS485=Val_0x0, CKEN=Val_0x0

Description

UART Control Register

Fields

CKEN	UART[5-0] Enable. One bit for each module. Bits[7-6] are reserved, bit 5 --> UART5, bit 0 --> UART0 0 (Val_0x0): Disable UART[5-0] module 1 (Val_0x1): Enable UART[5-0] module
CLK_SEL	UART[5-0]_SCLK Select. One bit for each module. Bits[15-14] are reserved, Bit 13 --> UART5, bit 8 --> UART0. 0 (Val_0x0): 38.4 MHz 1 (Val_0x1): SYST_PCLK clock
RS485	UART[5-4] RS485 Status. One bit for each module. Bits[23-22] are reserved, bit 21 --> UART5, bit 20 --> UART4. Bits[19-16] are reserved. 0 (Val_0x0): UART not in RS485 mode 1 (Val_0x1): UART is in RS485 mode
DMA_SEL	UART DMA select for UART[5-4]. Bits[27-26] are reserved, bit 24 --> UART4. 0 (Val_0x0): Select DMA0

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